Logic Design Engineer Santa Clara,CA CGEMJP00306774

1178056
  • Job type

    Contract
  • Location

    California
  • Profession

    Engineering
  • Industry

    Engineering
  • Pay

    Competitive Rates

New Contract Opportunity - Logic Design Engineer - Santa Clara, CA

Your new company
Our client is a global leader in consulting, digital transformation, technology, and engineering services. They specialize in delivering end-to-end solutions that empower businesses to navigate complex digital landscapes. With deep expertise across industries such as cloud computing, artificial intelligence, cybersecurity, and sustainable energy, they provide critical strategic, technical, and workforce support. Their global presence and commitment to innovation make them trusted partners for organizations seeking to accelerate growth and transformation.

Your new role
The RTL Engineer performs detailed block design from system requirements and evolving specifications. Perform RTL coding, Lint checks, CDC tests, creating timing constraint files. Working closely with Synthesis, STA, PD and DFT teams to meet all functional requirements, performance, power, and area goals.

  • Develop HW architecture from specification documents.
  • Take complete responsibilities include writing RTL code for IP development/RTL integration, checking the code for Lint/CDC issues, checking synthesizability and timing quality of the design, checking low power implementation, supporting verification team with debug and support physical design teams on timing constraints and other design topics using Verilog/System Verilog/VHDL.
  • Develop and execute low power design (UPF/CPF).
  • Design top-level RTL, integration of blocks, clocks, resets, configuration registers, etc.
  • Knowledge of JESD204C block design and related design/verification experience (includes licensed IP & PHY from 3rd parties)
  • Awareness of DFT concepts to be used to fix functional violations that may get introduced, which include DFT structures.
  • Carry out static checks including Lint/CDC (Spyglass), synthesis, LEC and STA. Debugging and fixing functional break.
  • Take ownership of tasks and drive tasks to closure.
What You'll Need to Succeed
  • Bachelor’s degree in electrical or computer engineering or related field
  • 7+ years of experience in Logic (RTL) Design
  • Great communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.
  • Experience with advanced peripheral bus IP’s such as GPIO, UART, SPI, SW, JTAG, and I2C.
  • Strong fundamentals in VLSI design
  • Strong problem-solving and data analysis skills
  • Strong skills using scripting languages such as Perl, TCL, Python.
  • Excellent interpersonal skills and able to work with remote teams
  • Influence tools, flows, and overall design methodology in design construction, signoff, and optimization with a data-driven approach.
  • Knowledge of low-speed bus protocols (AMBA/OCP) and high-speed serial protocols (PCIe/USB/Ethernet) will used at various stages of the design.

What You'll Get in Return
• Competitive rate
• Challenging and great work environment
• Employee engagement opportunities

What you need to do now
If you're interested in this role, click 'apply now' to forward an up-to-date copy of your CV, or call us now. If this job isn't quite right for you, but you are looking for a new position, please contact us for a confidential discussion on your career.



























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Talk to Trupti Sharma, the specialist consultant managing this position

Located in Tampa - Head Office, 4350 West Cypress St, Suite 1000Telephone:  6475033467