ASIC CAD/EDA Flow/Methodology Developer - San Jose - CGEMJP00306056
JOB_53321661177308Job type
ContractLocation
CaliforniaProfession
EngineeringIndustry
EngineeringPay
Competitive Rates
ASIC CAD/EDA Flow/Methodology Developer - Irvine/San Jose (CA), Minneapolis (MN), Phoenix/Chandler (AZ)
Your new company
Our client is a global leader in consulting, digital transformation, technology, and engineering services. They specialize in delivering end-to-end solutions that empower businesses to navigate complex digital landscapes. With deep expertise across industries such as cloud computing, artificial intelligence, cybersecurity, and sustainable energy, they provide critical strategic, technical, and workforce support. Their global presence and commitment to innovation make them trusted partners for organizations seeking to accelerate growth and transformation.
Your new role
Our client is a global leader in consulting, digital transformation, technology, and engineering services. They specialize in delivering end-to-end solutions that empower businesses to navigate complex digital landscapes. With deep expertise across industries such as cloud computing, artificial intelligence, cybersecurity, and sustainable energy, they provide critical strategic, technical, and workforce support. Their global presence and commitment to innovation make them trusted partners for organizations seeking to accelerate growth and transformation.
Your new role
- 8+ years of experience in analog/mixed-signal layout design of deep submicron CMOS circuits and at least 3+ years of recent experience on advanced nodes, including FinFET technologies.
- Great understanding of CAD flows and tools related to ASIC/SOC methodologies.
- Excellent programming skills in languages: SKILL, Perl; Python is a plus
- Strong fundamentals in software development.
- Knowledge with EMIR (RV), Physical design verification (DRC/LVS/PEX/ERC), waiver.
- Working knowledge of circuit design concepts such as device characteristics, SPICE and Verilog netlists and simulation.
- Excellent communication and interpersonal skills.
What You'll Need to Succeed
- Influence tools, flows, and overall design methodology in design construction, signoff, and optimization with a data-driven approach.
- Knowledge of signoff closure – Timing with SI and OCV, Power, IR and Physical Verification at both block and chip level.
- Experience in Block-level and Full-chip integration.
- Understanding constraints and fixing design/timing techniques.
- Interpreting LVS, DRC and ERC reports to find the fastest way to complete the layout.
- Utilizing advanced CAD tools and mask design knowledge to deliver a correct and robust layout that meets stringent matching performance, area, and power requirements.
- Understanding constraints and fixing design/timing techniques.
- Understanding SI prevention, fixing methodology and implementation.
- Proficient in Synopsys tools such as ICC/ICC2, Cadence Innovus/Virtuoso.
- Experience in Design Automation and UNIX systems.
• Competitive rate
• Challenging and great work environment
• Employee engagement opportunities
What you need to do now
If you're interested in this role, click 'apply now' to forward an up-to-date copy of your CV, or call us now.
If this job isn't quite right for you, but you are looking for a new position, please contact us for a confidential discussion on your career.
ASIC CAD/EDA Flow/Methodology Developer - San Jose - CGEMJP00306056JOB_533216611773082025-07-182025-10-17
Talk to Rupal Pandey, the specialist consultant managing this position
Located in Tampa - Head Office, Suite 1000, 4350 West Cypress StTelephone: 8013491315JOB_53321661177308